Asymmetric devices have drawn increasing attention as a method to suppress short channel effects in metal-oxide-silicon field effect transistors (MOSFETS). However, current technology forms asymmetrical devices by adding additional photolithographic process steps to existing methods. Additional photolithographic processes require additional photomasks and exposure tools and add additional time to the fabrication process, making such processes more costly and adversely effecting yield. Therefore, there is a need for a method of fabricating asymmetrical structures, including MOSFETs that do not require photolithographic steps to generate asymmetrical spacers.